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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">MPAM2_EL2, MPAM2 Register (EL2)</h1><p>The MPAM2_EL2 characteristics are:</p><h2>Purpose</h2>
        <p>Holds information to generate MPAM labels for memory requests when executing at EL2.</p>
      <h2>Configuration</h2><p>AArch64 System register MPAM2_EL2 bit [63] is architecturally mapped to AArch64 System register <a href="AArch64-mpam3_el3.html">MPAM3_EL3[63]</a> when EL3 is implemented.</p><p>AArch64 System register MPAM2_EL2 bit [63] is architecturally mapped to AArch64 System register <a href="AArch64-mpam1_el1.html">MPAM1_EL1[63]</a>.</p><p>This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAM2_EL2 are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>This register has no effect if EL2 is not enabled in the current Security state.</p>
      <h2>Attributes</h2>
        <p>MPAM2_EL2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-63_63">MPAMEN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-62_59">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-58_58-1">TIDR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-57_57">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-56_56-1">ALTSP_HFC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-55_55-1">ALTSP_EL2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-54_54-1">ALTSP_FRCD</a></td><td class="lr" colspan="3"><a href="#fieldset_0-53_51">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-50_50-1">EnMPAMSM</a></td><td class="lr" colspan="1"><a href="#fieldset_0-49_49">TRAPMPAM0EL1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-48_48">TRAPMPAM1EL1</a></td><td class="lr" colspan="8"><a href="#fieldset_0-47_40">PMG_D</a></td><td class="lr" colspan="8"><a href="#fieldset_0-39_32">PMG_I</a></td></tr><tr class="firstrow"><td class="lr" colspan="16"><a href="#fieldset_0-31_16">PARTID_D</a></td><td class="lr" colspan="16"><a href="#fieldset_0-15_0">PARTID_I</a></td></tr></tbody></table><h4 id="fieldset_0-63_63">MPAMEN, bit [63]</h4><div class="field">
      <p>MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.</p>
    <table class="valuetable"><tr><th>MPAMEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The default PARTID and default PMG are output in MPAM information from all Exception levels.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>MPAM information is output based on the MPAMn_ELx register for ELn according to the MPAM configuration.</p>
        </td></tr></table><p>If EL3 is not implemented, this field is read/write.</p>
<p>If EL3 is implemented, this field is read-only and reads the current value of the read/write <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.MPAMEN bit.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul><p>Accessing this field has the following behavior:</p><ul><li>When EL3 is not implemented, access to this field
                            is <span class="access_level">RW</span>.</li><li>
                Otherwise,
                
            access to this field
            is <span class="access_level">RO</span>.</li></ul></div><h4 id="fieldset_0-62_59">Bits [62:59]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-58_58-1">TIDR, bit [58]<span class="condition"><br/>When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMIDR_EL1.HAS_TIDR == 1:
                        </span></h4><div class="field">
      <p>TIDR traps accesses to <a href="AArch64-mpamidr_el1.html">MPAMIDR_EL1</a> from EL1 to EL2.</p>
    <table class="valuetable"><tr><th>TIDR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trap accesses to <a href="AArch64-mpamidr_el1.html">MPAMIDR_EL1</a> from EL1 to EL2.</p>
        </td></tr></table>
      <p><a href="AArch64-mpamhcr_el2.html">MPAMHCR_EL2</a>.TRAP_MPAMIDR_EL1 == 1 also traps <a href="AArch64-mpamidr_el1.html">MPAMIDR_EL1</a> accesses from EL1 to EL2. If either TIDR or TRAP_MPAMIDR_EL1 are 1, accesses are trapped.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-58_58-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-57_57">Bit [57]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-56_56-1">ALTSP_HFC, bit [56]<span class="condition"><br/>When FEAT_RME is implemented and MPAMIDR_EL1.HAS_ALTSP == 1:
                        </span></h4><div class="field">
      <p>Hierarchical force of alternative PARTID space controls. When <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 0, ALTSP controls in MPAM2_EL2 have no effect.  When MPAM3_EL3.ALTSP_HEN is 1, this bit selects whether the PARTIDs in <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a> and <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a> are in the primary (0) or alternative (1) PARTID space for the security state.</p>
    <table class="valuetable"><tr><th>ALTSP_HFC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>When <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 1, the PARTID space of <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a>.PARTID_I, <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a>.PARTID_D, <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a>.PARTID_I, and <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a>.PARTID_D are in the primary PARTID space for the Security state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 1, the PARTID space of <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a>.PARTID_I, <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a>.PARTID_D, <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a>.PARTID_I, and <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a>.PARTID_D are in the alternative PARTID space for the Security state.</p>
        </td></tr></table><p>This control has no effect when <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 0.</p>
<p>For more information, see 'Alternative PARTID spaces and selection' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598).</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-56_56-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-55_55-1">ALTSP_EL2, bit [55]<span class="condition"><br/>When FEAT_RME is implemented and MPAMIDR_EL1.HAS_ALTSP == 1:
                        </span></h4><div class="field">
      <p>Select alternative PARTID space for PARTIDs in MPAM2_EL2 when <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 1.</p>
    <table class="valuetable"><tr><th>ALTSP_EL2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>When <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 1, selects the primary PARTID space for MPAM2_EL2.PARTID_I and MPAM2_EL2.PARTID_D.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When <a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>.ALTSP_HEN is 1, selects the alternative PARTID space for MPAM2_EL2.PARTID_I and MPAM2_EL2.PARTID_D.</p>
        </td></tr></table>
      <p>For more information, see 'Alternative PARTID spaces and selection' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598).</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-55_55-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-54_54-1">ALTSP_FRCD, bit [54]<span class="condition"><br/>When FEAT_RME is implemented and MPAMIDR_EL1.HAS_ALTSP == 1:
                        </span></h4><div class="field">
      <p>Alternative PARTID forced for PARTIDs in this register.</p>
    <table class="valuetable"><tr><th>ALTSP_FRCD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The PARTIDs in this register are using the primary PARTID space.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The PARTIDs in this register are using the alternative PARTID space.</p>
        </td></tr></table><p>This bit indicates that a higher Exception level has forced the PARTIDs in this register to use the alternative PARTID space defined for the current Security state. In EL2, it is also 1 when MPAM2_EL2.ALTSP_EL2 is 1.</p>
<p>For more information, see 'Alternative PARTID spaces and selection' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598).</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-54_54-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-53_51">Bits [53:51]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-50_50-1">EnMPAMSM, bit [50]<span class="condition"><br/>When FEAT_SME is implemented:
                        </span></h4><div class="field">
      <p>Traps execution at EL1 of instructions that directly access the <a href="AArch64-mpamsm_el1.html">MPAMSM_EL1</a> register to EL2. The exception is reported using ESR_ELx.EC value <span class="hexnumber">0x18</span>.</p>
    <table class="valuetable"><tr><th>EnMPAMSM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control causes execution of these instructions at EL1 to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause execution of any instructions to be trapped.</p>
        </td></tr></table>
      <p>This field has no effect on accesses to <a href="AArch64-mpamsm_el1.html">MPAMSM_EL1</a> from EL2 or EL3.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-50_50-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-49_49">TRAPMPAM0EL1, bit [49]</h4><div class="field">
      <p>Trap accesses from EL1 to the <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a> register trap to EL2.</p>
    <table class="valuetable"><tr><th>TRAPMPAM0EL1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses to <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a> from EL1 are not trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Accesses to <a href="AArch64-mpam0_el1.html">MPAM0_EL1</a> from EL1 are trapped to EL2.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When EL3 is not implemented,
            this field resets to
            <span class="binarynumber">1</span>.
</li>
          
            <li>When EL3 is implemented,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><h4 id="fieldset_0-48_48">TRAPMPAM1EL1, bit [48]</h4><div class="field">
      <p>Trap accesses from EL1 to the <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a> register trap to EL2.</p>
    <table class="valuetable"><tr><th>TRAPMPAM1EL1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses to <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a> from EL1 are not trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Accesses to <a href="AArch64-mpam1_el1.html">MPAM1_EL1</a> from EL1 are trapped to EL2.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When EL3 is not implemented,
            this field resets to
            <span class="binarynumber">1</span>.
</li>
          
            <li>When EL3 is implemented,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><h4 id="fieldset_0-47_40">PMG_D, bits [47:40]</h4><div class="field">
      <p>Performance monitoring group for data accesses.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-39_32">PMG_I, bits [39:32]</h4><div class="field">
      <p>Performance monitoring group for instruction accesses.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-31_16">PARTID_D, bits [31:16]</h4><div class="field">
      <p>Partition ID for data accesses, including load and store accesses, made from EL2.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_0">PARTID_I, bits [15:0]</h4><div class="field">
      <p>Partition ID for instruction accesses made from EL2.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing MPAM2_EL2</h2>
        <p>None of the fields in this register are permitted to be cached in a TLB.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, MPAM2_EL2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b1010</td><td>0b0101</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
            if Halted() &amp;&amp; EDSCR.SDD == '1' then
                UNDEFINED;
            else
                AArch64.SystemAccessTrap(EL3, 0x18);
        else
            AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        X[t, 64] = MPAM2_EL2;
elsif PSTATE.EL == EL3 then
    X[t, 64] = MPAM2_EL2;
                </p><h4 class="assembler">MSR MPAM2_EL2, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b100</td><td>0b1010</td><td>0b0101</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; HCR_EL2.NV == '1' then
        if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
            if Halted() &amp;&amp; EDSCR.SDD == '1' then
                UNDEFINED;
            else
                AArch64.SystemAccessTrap(EL3, 0x18);
        else
            AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        MPAM2_EL2 = X[t, 64];
elsif PSTATE.EL == EL3 then
    MPAM2_EL2 = X[t, 64];
                </p><h4 class="assembler">MRS &lt;Xt&gt;, MPAM1_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b1010</td><td>0b0101</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() &amp;&amp; MPAM2_EL2.TRAPMPAM1EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV1,NV&gt; == '111' then
        X[t, 64] = NVMem[0x900];
    else
        X[t, 64] = MPAM1_EL1;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HCR_EL2.E2H == '1' then
        X[t, 64] = MPAM2_EL2;
    else
        X[t, 64] = MPAM1_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = MPAM1_EL1;
                </p><h4 class="assembler">MSR MPAM1_EL1, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b1010</td><td>0b0101</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() &amp;&amp; MPAM2_EL2.TRAPMPAM1EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV1,NV&gt; == '111' then
        NVMem[0x900] = X[t, 64];
    else
        MPAM1_EL1 = X[t, 64];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; MPAM3_EL3.TRAPLOWER == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HCR_EL2.E2H == '1' then
        MPAM2_EL2 = X[t, 64];
    else
        MPAM1_EL1 = X[t, 64];
elsif PSTATE.EL == EL3 then
    MPAM1_EL1 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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